As a Master’s thesis student, you will:
- Develop a MATLAB ↔ FPGA Ethernet communication interface for transmitting raw samples and control messages.
- Implement bare‑metal or minimal runtime on Zynq to avoid OS overhead and ensure deterministic packet flow.
- Explore the use of a secondary SFP/Ethernet interface for debug packet capture.
- Validate RF/PHY functionality by comparing FPGA output with MATLAB models.
- Deliver a reusable HIL setup supporting future system bring-up and prototyping.
- Verify/Validate the system with cocotb.
- Final-year Master of Engineering (EE/Embedded/FPGA).
- FPGA design (VHDL/Verilog) and building testbenches with cocotb.
- MATLAB scripting and modeling.
- Good understanding of digital communications.
- Basic knowledge of Ethernet networking.
Nice to have: Zynq/Vivado experience, bare‑metal programming, AXI interfaces, Digital communication basics.
What You Will Learn🚀- FPGA system design and real-time communication.
- Zynq SoC development (RTL + bare-metal software).
- MATLAB–FPGA co-simulation workflows.
- Ethernet protocols and packet interface design.
- RF/PHY-level testing and validation methodology.
Why This Project Matters
This HIL framework will remove slowdowns caused by cross‑team dependencies and long hardware bring-up cycles. MATLAB modeling takes days, while FPGA development can take weeks or months—this project enables both to progress independently and much faster.
If you're enthusiastic about FPGA, communication systems, and hands-on real hardware development, we want to hear from you!
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